The present invention relates generally to memory devices, and more particularly to a memory array architecture that supports block write operation.
Memory devices are integral to a computer system, and to many electronic circuits. Continuous improvements in the operating speed and computing power of a central processing unit (CPU) enables operation of an ever-greater variety of applications, many of which require faster and larger memories. Larger memories can be obtained by shrinking the geometry of the memory cells and data lines within memory devices. However, with regard to memory speed, the access time for a memory device is generally governed by certain limitations. More particularly, memory speed is, to a large extent, dictated by the charge and discharge rates of parasitic capacitance on internal data lines.
Conventionally, a memory access to write a data bit is performed by: (1) activating a row control line (or word line) for the required memory location; (2) receiving a write command and the data bit; (3) activating a column select line; and (4) providing the data bit to the memory cell. Conventionally, these steps are performed in sequential order for each accessed data bit. These steps also define the access time of a memory device (i.e., to write a data bit) which, in turn, determines the data transfer rate.
Incremental improvements in the data transfer rate for a memory write can be achieved by reducing the charge time of the internal data lines. The charge time can be improved by shrinking the geometry of the device, thus reducing the parasitic effects. Substantial improvement in the data transfer rate can be achieved by performing a concurrent write of a block of data bits to the memory device.
Several conventional memory array architectures support block write operation. One architecture uses a single write driver that concurrently drives a set of bit lines in the memory array. This design requires a large write driver having the capability to drive all connected bit lines. For example, to support an 8-bit block write operation the write driver is designed to concurrently drive eight bit lines. This design is also inflexible since it writes the same data bit to all connected bit lines.
A second architecture alleviates some of the problems associated with the first architecture by using multiple (e.g., two) write drivers. Each write driver drives a smaller number of bit lines and can be designed with lower drive capability. Multiple write drivers also allow multiple data bits to be concurrently written to the memory array. For example, a design with two write drivers can divide an 8-bit block write operation into two 4-bit block write operations performed by the two write drivers. The second design is an improvement over the first design but requires additional circuitry and internal data lines.
The additional circuitry and internal data lines, while necessary to support block writes of multiple data bits to multiple memory locations, result in a larger circuit die area and increased cost. The increased die area is essentially a xe2x80x9cdie penaltyxe2x80x9d for the ability to concurrently write a block of data bits to memory. As can be seen, a memory array architecture that supports block write operations with minimal die and cost penalties is highly desirable.
The invention provides a memory array architecture that supports block write operation and has many advantages over conventional memory array architectures while incurring a small xe2x80x9cdie penalty.xe2x80x9d The invention achieves this by partitioning a memory array into segments. With N segments, the memory array supports a block write of up to N data bits to memory with minimal performance degradation, if at all.
A specific embodiment of the invention provides a memory device that includes at least one memory array. Each memory array is partitioned into a number of segments. Each segment includes one or more bit lines. Each segment is further associated with a local input/output (I/O) line that couples to zero or more bit lines within that segment. The bit lines are coupled to the local I/O line by controlling one or more column select lines associated with that segment. Each segment is also associated with a write driver that couples to the local I/O line. Each local I/O line has a length that is a portion of the length of the memory array. A block write operation is performed by concurrently driving one or more write drivers (up to N write drivers). Each write driver drives the bit line(s) coupled to the local I/O line(s) associated with that write driver.
The local I/O lines associated with each memory array can be designed to have similar lengths. Further, the combined lengths of the local I/O lines associated with a memory array can be approximately equal to the length of the memory array. These characteristics reduce die area and can improve performance.
In an embodiment, each write driver drives a single bit line at any given moment. This embodiment provides similar performances for a block write and a xe2x80x9cnormalxe2x80x9d write to a single bit line. In another embodiment, each write driver can be designed to concurrently drive multiple bit lines to allow for a larger sized block write than the number of available write drivers.
The invention also supports a double data rate (DDR) block write operation. The DDR block write allows a 2M block write to be achieved by writing to one group of M bit lines during a first clock phase (e.g., the rising edge) and to another group of M bit lines during a second clock phase (e.g., the falling edge). The block write operation can be initiated upon receiving masking information for the bit lines.
The foregoing, together with other aspects of this invention, will become more apparent when referring to the following specification, claims, and accompanying drawings.